Welcome![Sign In][Sign Up]
Location:
Search - image processing in vhdl

Search list

[File FormatdesignforvideobasedonSDRAM

Description: 在信息处理中,特别是实时视频图像处理中,通常都要对实现视频图像进行处理,而这首先必须设计大容量的存储器,同步动态随机存储器SDRAM虽然有价格低廉、容量大等优点,但因SDRAM的控制结构复杂,常用的方法是设计SDRAM通用控制器,这使得很多人不得不放弃使用SDRAM而使用价格昂贵的SRAM。为此,笔者在研究有关文献的基础上,根据具体情况提出一种独特的方法,实现了对SDRAM的控制,并通过利用FPGA控制数据存取的顺序来实现对数字视频图像的旋转,截取、平移等实时处理。-In information processing, especially real-time video image processing usually have to deal with video images, which must first be designed large-capacity memory, synchronous dynamic random access memory SDRAM Although there are low cost, large capacity, etc., but SDRAM control structure of the complex, commonly used method is to design generic SDRAM controller, which makes a lot of people had to abandon the use of SDRAM and the use of expensive SRAM. To this end, the authors examine the literature based on the specific situation in a unique way to realize the control of SDRAM, and control data through the use of FPGA to realize the order of access to digital video image rotation, interception, translation, such as real-time processing.
Platform: | Size: 137216 | Author: 赵明玺 | Hits:

[VHDL-FPGA-Verilogdjdcf

Description: 在3D图像处理等对运算要求高的领域,高效除法器已成为处理器内必不可少的部件。在分析除法器设计的泰勒级数展开算法基础上,提出了一种新的除法器设计算法。在满足同样精度的情况下,所实现的三级流水线的除法器,与基于泰勒级数展开算法的除法器相比,面积更小,速度更快。-In 3D image processing and so on, demanding area of computing, efficient divider has become essential components inside the processor. In analyzing the divider design Taylor series expansion algorithm based on a new design algorithm divider. Meet the same accuracy in the cases, the three realize the divider line, and based on the Taylor series expansion algorithm divider compared to a smaller area, faster.
Platform: | Size: 157696 | Author: usbusb01 | Hits:

[Special Effectsthe.implement.of.image.pretreatment.algorithm.in.t

Description: 现场可编程逻辑门阵列在实时数字图像处理中的应用-Field-programmable gate array logic in real-time digital image processing
Platform: | Size: 159744 | Author: 刘文娟 | Hits:

[VHDL-FPGA-VerilogFPGA

Description: HDTV视频内容创作的繁荣以及在带宽受限的广播信道环境中传送这些视频内容的方法,不断催生新的视频压缩标准和相关视频图像处理设备。-HDTV video content creation and prosperity as well as bandwidth-constrained environment of the broadcasting channel to send video content of these methods, birth of a new video compression standards and associated video image processing equipment.
Platform: | Size: 59392 | Author: chenqunqin | Hits:

[Special Effectsthe_stud_of_high-speed_image_processing_for_machin

Description: 机器视觉中高速图象处理方法的研究以及FPGA的实现-Machine vision in the high-speed image processing methods, as well as the realization of FPGA
Platform: | Size: 2932736 | Author: 许小姐 | Hits:

[VHDL-FPGA-VerilogSRAM-PINGPANG

Description: 超声视频图像需要实时地采集并在处理后在显示器上重建,图像存储器就必须不断地写入数据,同时又要不断地从存储器读出数据送往后端处理和显示[11]。为了满足这种要求,可以在采集系统中设置2片容量一样的SRAM,通过乒乓读写机制来管理。任何时刻,只能有1片SRAM处于写状态,同时也只有1片SRAM处于读状态。工作期间,2片SRAM都处于读写状态轮流转换的过程,转换的过程相同,但是状态错开,从而保证数据能连续地写人和读出祯存.-Real-time ultrasound video images need to collect and deal with the reconstruction after the display, image memory must be continually write data, while at the same time continuously sent from the memory读出数据back-end processing and display [11]. To meet this requirement, you can set up collection system capacity of two different SRAM, read and write through the ping-pong mechanisms to manage. At any time, can only have a SRAM in write state, but also the only one at a time the state of SRAM. Work, two SRAM read and write are in the process of converting a state of rotation, the conversion process of the same, but the state staggered to ensure that data can be continuously written and read out Qizhen depositors.
Platform: | Size: 1024 | Author: smj1980 | Hits:

[VHDL-FPGA-VerilogFPGAbi_ioreseach

Description: :针对现场可编程门阵列(FPGA)芯片的特点,研究FPGA中双向端口I/O的设计,同时给 出仿真初始化双向端口I/O的方法。采用这种双向端口的设计方法,选用Xilinx的Spartan2E芯片 设计一个多通道图像信号处理系统。-: For field programmable gate array (FPGA) chip features of FPGA in the bi-directional port I/O design, the simulation is initialized at the same time two-way port I/O method. Using this design method of two-way ports, optional Spartan2E the Xilinx chip to design a multi-channel image signal processing system.
Platform: | Size: 115712 | Author: zhanyi | Hits:

[Special EffectsRead

Description: 这是一个有关实时模拟和数字图像处理的fpga程序-This is a real-time analog and digital image processing procedures for the FPGA
Platform: | Size: 1024 | Author: cjgqf | Hits:

[Other23

Description: 图像技术的应用 : 包括:基于FPGA的图像处理系统; 基于图像特征的景象匹配辅助导航系统中的关键技术研究; 图像导航技术的发展和应用 -Application of imaging technology: including: FPGA-based image processing system images based on image feature matching assisted navigation system in the research of key technologies image navigation technology development and application of
Platform: | Size: 4107264 | Author: 李灵 | Hits:

[Special Effectsvideo_process_base_on_DSPandFPGA

Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型 化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了 三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
Platform: | Size: 546816 | Author: John | Hits:

[Software EngineeringDigital_Filter_implementation_by_FPGA

Description: 1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis 2. fpga implemention of a median filter 3. fpga implementation of digital filters 4.hardware acceleration of edge detection algorithm on fpgas 5.implementation and evaluation of image processing algorithms on reconfigurable architecture using C-based hardware descriptive languages 6. implementing 2D median filter in fpgas 7.视频图像处理与分析的网络资源
Platform: | Size: 1969152 | Author: carol | Hits:

[VHDL-FPGA-Verilogfilter

Description: 图像处理技术中3*3模板的滤波电路的VHDL实现.-Image processing technology in the 3* 3 template VHDL implementation of the filter circuit.
Platform: | Size: 292864 | Author: 翁文天 | Hits:

[VHDL-FPGA-Verilogedge

Description: 图像处理中边缘检测的VHDL源代码,所用的算法是garbor变换-Image processing edge detection of VHDL source code, the algorithms used are garbor transform
Platform: | Size: 384000 | Author: 翁文天 | Hits:

[VHDL-FPGA-Verilogmedian_filterCode

Description: 采用快速中指滤波算法实现图像的中值滤波,使用VHDL语言ISE环境-Image Median Filter
Platform: | Size: 12288 | Author: 若谙 | Hits:

[Other Embeded programCCD_senior_design_final_report

Description: 一个基于FPGA和CCD的视觉处理硬件平台项目开发文档-The design is a first step towards a hardware implementation of the super-resolution algorithms and other multimedia projects.The design presented in this paper may be used as a platform for many multimedia and image processing projects.
Platform: | Size: 483328 | Author: neversee | Hits:

[OtherUBS_24Jun09

Description: this document is about image processing in vhdl
Platform: | Size: 5120 | Author: Manikandan | Hits:

[VHDL-FPGA-VerilogFPGA_ImageProcessing

Description: Implementation of Image Processing Algorithms in FPGA Hardware.
Platform: | Size: 105472 | Author: Sooraj | Hits:

[VHDL-FPGA-VerilogFPGA_image

Description: fpga实现图像处理,JPEG标准下图象压缩,VHDL语言编程。-fpga implementation image processing, JPEG image compression under the standard, VHDL language programming.
Platform: | Size: 295936 | Author: xiangchuiyi | Hits:

[Industry researchdfbfdvbfdbfgbfgb153351bgfb

Description: : 条形码识别,直接运行程序即可; pdf417lib:二维条形码打印(输出为ps格式的文件),在书中第6章二维条形码打印部分有程序使用的说明; 条形码生成器源程序:生成一维条形码,直接运行程序即可; [8位数字频率计.rar] - 数字频率计~ VHDL 实现 可以实现频率的测量和现实的功能 8位 [hot.rar] - 图像分割是数字图像处理中的关键技术之一。图像分割是将图像中有意义的特征-tiaoxingma.rar]- barcode: barcode recognition, you can run the program directly pdf417lib: two-dimensional bar code printing (output ps format), in the book, Chapter 6, two-dimensional bar code printing part of a program using the instructions barcode generation device source: Build a one-dimensional bar code, you can run the program directly [8-bit digital frequency meter. rar]- digital frequency meter ~ VHDL implementation can be achieved and actual measurement of the frequency function of 8 [hot.rar]- Image Segmentation digital image processing of the key technologies. Image segmentation is the image characteristics of a meaningful
Platform: | Size: 1087488 | Author: ihba | Hits:

[Graph programDE2_70_D5M_LTM_black-line

Description: 基于DE2-70的摄像头图像处理程序,主要在边缘检测上增加了视线内黑线判断的功能-Based on the DE2-70 camera image-processing program, mainly in the edge detection increased the black line within the line of sight to determine the function
Platform: | Size: 6322176 | Author: liliang | Hits:
« 12 »

CodeBus www.codebus.net